// **************************************************************
// COPYRIGHT(c)2021, Xidian University
// All rights reserved.
//
// IP LIB INDEX : 
// IP Name      : 
//                
// File name    :axis_conv_rx_40
// Module name  : 
// Full name    :
//
// Author       :  Hbing 
// Email        :  928130120@qq.com
// Data         :  2021/7/8
// Version      :  V 1.0 
// 
//Abstract      :
// Called by    :  Father Module
// 
// Modification history
// ------------------------------------------------------------------------------------------------------
// 
//  
// *********************************************************************
 `include "top_define.v"
// *******************
// *******************
// DESCRIPTION
// *******************
// 40G½ÓÊÕ´¦µÄaxis¿çÊ±ÖÓfifo
// clk 312.5 -> 156.25 or 312.5 -> 630
// axi_data_width 256 -> 256
// TIMESCALE
// ******************* 
`timescale 1ns/1ps 

module axis_conv_rx(

	input  wire			m_axis_areset 	,
	input  wire  			m_axis_aclk 	,
		
    input  wire  [11:0]ram_dp_cfg_register,

	input  wire 			m_axis_rtvalid	,
	output wire 			m_axis_rtready	,
	input  wire [255:0]		m_axis_rtdata 	,
	input  wire [ 31:0]		m_axis_rtkeep 	,
	input  wire 			m_axis_rtlast 	,
		
	input  wire 			s_axis_aclk 	,
	input  wire 			s_axis_areset 	,
		
	output reg  			s_axis_rtvalid 	,
	input  wire 			s_axis_rtready 	,
	output reg  [255:0]		s_axis_rtdata  	,
	output reg  [ 31:0]		s_axis_rtkeep  	,
	output reg  			s_axis_rtlast  	
	);

//*******************
//DEFINE PARAMETER
//*******************
//Parameter(s) 

//*********************
//INNER SIGNAL DECLARATION
//*********************
//REGS

reg 			m_axis_rtvalid_sample		;
reg [255:0]		m_axis_rtdata_sample 		;
reg [ 31:0]		m_axis_rtkeep_sample 		;
reg 			m_axis_rtlast_sample 		;

reg  			fifo_rd 					;
//reg             fifo_empty_ff               ;
//reg             fifo_rd_ff                  ;
reg             fifo_data_rd_temp_ff        ;
reg 			s_axis_rtvalid_fifo		    ;
reg [255:0]	    s_axis_rtdata_fifo 		    ;
reg [ 31:0]	    s_axis_rtkeep_fifo 		    ;
reg 			s_axis_rtlast_fifo 		    ;
//*********************    
    
//WIRES	    
wire [290:0] 	fifo_din 				    ;
wire [290:0] 	fifo_dout  				    ;
wire 			fifo_empty 				    ;
wire 			fifo_full 				    ;
wire            fifo_data_rd_temp           ;
//INSTANTCE MODULE    
//*********************
assign fifo_din = {1'b0,m_axis_rtlast_sample,m_axis_rtvalid_sample,m_axis_rtkeep_sample,m_axis_rtdata_sample};
// assign {s_axis_rtlast_fifo,s_axis_rtvalid_fifo,s_axis_rtkeep_fifo,s_axis_rtdata_fifo} = fifo_dout[289:0];

assign m_axis_rtready = ~fifo_full;

//·ÇÊ××ÖÖÃ³öFIFO
`ifdef ASIC
asyn_fifo_nw256_nb291 #(.L(8),.DW(291))
U_asyn_fifo_nw256_nb291 (
	.clka(m_axis_aclk),
	.clkb(s_axis_aclk),
    .ram_dp_cfg_register(ram_dp_cfg_register),
	.clr(m_axis_areset),
	.w_data(fifo_din),
	.w_we(m_axis_rtvalid_sample),
	.w_full(),
	.w_afull(fifo_full),
	.r_data(fifo_dout),
	.r_re(fifo_data_rd_temp),
	.r_empty(fifo_empty),
	.r_aempty()
	);
`else
asyn_fifo_nw256_nb291 U_asyn_fifo_nw256_nb291(
	.wr_clk 		(m_axis_aclk 		 	),
	.wr_rst 		(~m_axis_areset 	 	),
	.din 			(fifo_din 			 	),
	.wr_en			(m_axis_rtvalid_sample 	),
	.full 			(fifo_full 				),
	.rd_clk 		(s_axis_aclk 			),
	.rd_rst 		(~s_axis_areset 	 	),
	.dout			(fifo_dout 				),
	.rd_en 			(fifo_data_rd_temp     	),
	.empty 			(fifo_empty 			)
	);
`endif

//*********************
//MAIN CORE
//*********************

//----------------------------------------------------
//                    Ô´Ê±ÖÓÓòÊý¾ÝÊäÈë
//----------------------------------------------------
//²úÉúÐ´Ê¹ÄÜ£¬½«Êý¾Ý´òÅÄºÍÐ´Ê¹ÄÜÍ¬²½
always @(posedge m_axis_aclk or negedge m_axis_areset) begin : sample_axi_stream
	if (~m_axis_areset) begin
		// reset
		m_axis_rtvalid_sample 	<=    1'b0;
		m_axis_rtdata_sample  	<= 	256'b0;
		m_axis_rtkeep_sample  	<=   32'b0;
		m_axis_rtlast_sample  	<=    1'b0; 
	end
	else if(m_axis_rtready) begin
		m_axis_rtdata_sample 	<= m_axis_rtdata 	;
		m_axis_rtkeep_sample	<= m_axis_rtkeep 	;
		m_axis_rtlast_sample	<= m_axis_rtlast 	;
		m_axis_rtvalid_sample   <= m_axis_rtvalid 	;
    end
	else begin
		m_axis_rtdata_sample 	<= m_axis_rtdata_sample  ;
		m_axis_rtkeep_sample	<= m_axis_rtkeep_sample	 ;
		m_axis_rtlast_sample	<= m_axis_rtlast_sample	 ;
		m_axis_rtvalid_sample   <= m_axis_rtvalid_sample ;
	end
end
//----------------------------------------------------
//                 Ä¿µÄÊ±ÖÓÓòÊä³ö
//----------------------------------------------------
//²úÉú¶ÁÊ¹ÄÜ£¬·Ç¿Õ¼´¶Á
always @(posedge s_axis_aclk or negedge s_axis_areset) begin : read_fifo
	if (~s_axis_areset) begin
		// reset
		fifo_rd 	<=    	1'b0;
	end
	else if(~fifo_empty && s_axis_rtready /*&& (~s_axis_rtlast_fifo)*/ /*&& s_axis_rtvalid_fifo*/) begin
		fifo_rd 	<=		1'b1;
	end
	else begin
		fifo_rd 	<= 		1'b0;
	end
end

assign fifo_data_rd_temp = fifo_rd & (~fifo_empty);

//always @(posedge s_axis_aclk or negedge s_axis_areset) begin
//	if(~s_axis_areset) begin
//		fifo_rd_ff <= 0;
//	end else begin
//		fifo_rd_ff <= fifo_rd;
//	end
//end

always @(posedge s_axis_aclk or negedge s_axis_areset) begin
	if(~s_axis_areset) begin
		fifo_data_rd_temp_ff <= 0;
	end else begin
		fifo_data_rd_temp_ff <= fifo_data_rd_temp;
	end
end

// //Ä¿µÄÊ±ÖÓÓòÊý¾ÝÊä³ö
always @(*) begin
		s_axis_rtvalid_fifo = fifo_dout[288]; 
        s_axis_rtdata_fifo  = fifo_dout[255:0]; 
        s_axis_rtkeep_fifo  = fifo_dout[287:256]; 
        s_axis_rtlast_fifo  = fifo_dout[289];
end

always @(posedge s_axis_aclk or negedge s_axis_areset) begin
	if(~s_axis_areset) begin
		s_axis_rtvalid <= 0;
        s_axis_rtdata  <= 0;
        s_axis_rtkeep  <= 0;
        s_axis_rtlast  <= 0;
	end 
	else if(fifo_data_rd_temp_ff)begin
		s_axis_rtvalid <= s_axis_rtvalid_fifo;
        s_axis_rtdata  <= s_axis_rtdata_fifo ;
        s_axis_rtkeep  <= s_axis_rtkeep_fifo ;
        s_axis_rtlast  <= s_axis_rtlast_fifo ;
	end
	else begin
		s_axis_rtvalid <= 0;
        s_axis_rtdata  <= 0;
        s_axis_rtkeep  <= 0;
        s_axis_rtlast  <= 0;
	end	
end
//·ÇÊ××ÖÖÃ³öFIFO
//always @(posedge s_axis_aclk or negedge s_axis_areset) begin
//	if(~s_axis_areset) begin
//		fifo_empty_ff <= 0;
//	end else begin
//		fifo_empty_ff <= fifo_empty;
//	end
//end

endmodule
